1. Field of the Invention
The invention relates to the field of semiconductor devices and fabrication processes and, in particular, to multi-gate vertical FinFET CMOS devices formed in a silicon-on-insulator (SOI) technology with improved avoidance of short channel effects, such as reduced drain induced barrier lowering (DIBL) and a method for fabricating the same.
2. Description of the Related Art
There is an ever-present desire in the semiconductor fabrication industry to achieve individual devices with smaller physical dimensions. Reducing the dimensions of devices is referred to as scaling. Scaling is desirable in order to increase the number of individual devices that can be placed on a given area of semiconductor material and the process yield and to reduce the unit cost and the power consumption of individual devices. In addition, scaling can result in performance increases of the individual devices as the charge carriers, having a finite velocity, have a shorter distance to travel and less bulk material has to accumulate or dissipate charges. Thus, the trend in the industry is towards thinner device regions and gate oxides, shorter channels, and lower power consumption.
However, scaling often creates some performance drawbacks. In particular, a known category of performance limitations known as short channel effects arises as the length of the channel of CMOS devices is reduced by scaling. One particular short-channel effect in CMOS devices, known as Drain Induced Barrier Lowering (DIBL), is significantly responsible for the degradation of sub-threshold swing in deep submicron devices. DIBL is a reduction in the potential barrier between the drain and source as the channel length shortens. When the drain voltage is increased, the depletion region around the drain increases and the drain region electric field reduces the channel potential barrier which results in an increased off-state or leakage current between the source and drain.
In planar CMOS devices, a retrograde channel dopant profile can be effectively used to control DIBL. In a CMOS process, n-type and p-type wells are created for NMOS and PMOS devices. In a conventional diffusion process, dopant concentration profiles in these n- and p-type wells are at a peak near the surfaces and decrease in the depth direction into the bulk as illustrated in FIG. 1. A retrograde profile is one in which the peak of the dopant concentration profile is not at the surface but at some distance into the bulk as shown in FIG. 2. Such retrograde profiles are helpful in deep submicron CMOS devices since they reduce the lowering of the source/drain barrier when the drain is biased high and when the channel is in weak inversion. This limits the amount of subthreshold leakage current flowing into the drain while maintaining the capacity for desired on-state current. A lower level of subthreshold leakage current provides improved circuit reliability and reduced power consumption.
A retrograde dopant profile also typically results in a lower dopant concentration near the surface of the wafer which reduces junction capacitances. Reduced junction capacitances allow the device to switch faster and thus increase circuit speed. Typically, retrograde profile dopant implants are done after formation of the gate. A halo (or pocket) implant is another known method used in deep submicron CMOS devices to reduce DIBL.
However in some applications, such as in an SOI process, it is difficult to create a retrograde profile due to the thinness of the silicon layer and the tendency of the dopants to diffuse. SOI processes employ a buried insulating layer, typically of silicon dioxide with a very thin silicon (Si) film (typically <1600 Å) overlying the oxide in which the active devices are formed. One difficulty encountered in SOI processes is that increasing the Si film thickness to facilitate forming a retrograde profile will increase the extent to which the devices formed therein get partially depleted. SOI devices also suffer from ‘floating body’ effects since, unlike conventional CMOS, in SOI there is no known easy way to form a contact to the bulk in order to remove the bulk charges.
Another difficulty is that when as-implanted retrograde dopant profiles diffuse during subsequent heat cycles in a process, they tend to spread out and lose their ‘retrograde’ nature to some extent. In SOI, since the silicon film is very thin, creating and maintaining a true retrograde dopant profile is very difficult. This is true even while using higher atomic mass elements like Indium (In) for NMOS and Antimony (Sb) as channel dopants. Diffusivity of these dopants in silicon is known to be comparable to lower atomic mass elements like boron (B) and phosphorus (P), when the silicon film is very thin, as in an SOI technology. Moreover, leakage current levels are known to increase when Indium is used for channel dopants (See “Impact of Channel Doping and Ar Implant on Device Characteristics of Partially Depleted SOI MOSFETs”, Xu et al., pp. 115 and 116 of the Proceedings 1998 IEEE International SOI Conference, October, 1998 and “Dopant Redistribution in SOI during RTA: A Study on Doping in Scaled-down Si Layers”, Park et al. IEDM 1999 pp. 337–340, incorporated herein by reference).
One device architecture that has been developed as an alternative to conventional planar CMOS while still achieving the benefits of scaling is known as a FinFET structure. A FinFET employs a vertically arranged structure or fin interposed between the source and drain where the channel is defined, typically with a multi-gate configuration. The advantages of the FinFET architecture include the ability to define device dimensions smaller than the photolithographic limit and the ability to easily access opposed sides of the channel to achieve a multi-gate structure. Such a multi-gate arrangement provides superior control over the gate of the device. A fully depleted silicon fin can be achieved with very low doping levels in the active region. However, short channel effects and effective control of threshold voltages still remains a challenge with the FinFET architecture.
From the foregoing it can be appreciated that there is an ongoing need for a method of fabricating deep submicron FinFET devices while reducing short channel effects such as DIBL and increasing device performance. There is a further need for reducing DIBL in deep submicron CMOS devices without incurring significant additional processing steps and high temperature processing.